# Copyright 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: MIT

#
#  AMD open Silicon Initialization Library
#
#
# PLATFORM Description Settings
#
#
# The following items are placed in the platform address map by the
# porting Engineer. These locations must be propogated into openSIL.
#
CONFIG_PLAT_APOB_ADDRESS=0x4000000
CONFIG_PSP_BIOS_BIN_BASE=0x76D00000
CONFIG_PSP_BIOS_BIN_SIZE=0x300000
CONFIG_PLAT_CPU_MICROCODE_LOCATION=0x003FFF00
CONFIG_PLAT_NUMBER_SOCKETS=1
# end of PLATFORM Description Settings

#
# AMD Processor(s) Selection
#

#
#  This is the list of supported AMD processors for openSIL. Please
#  select the Socket and processor designed into your motherboard.
#
CONFIG_MKT_SEG_SERVER=y
CONFIG_PLAT_MARKET_SEGMENT_NAME="Data Center"
CONFIG_SKT_TYPE_SP5=y
# CONFIG_SKT_TYPE_SP5 is set
CONFIG_PLAT_SOCKET_TYPE_NAME="SP5"
# CONFIG_SOC_F19M10 is set
CONFIG_SOC_F19M10=y
# end of AMD Processor(s) Selection

#
# AMD Silicon Feature Settings
#
#  The available silicon devices and features are dependent upon
#  which AMD processor(s) have been selected for inclusion into
#  the platform build.
#
CONFIG_HAVE_CCX_ZEN4=y

#
# Compute Core Complex (CCX) Device
#
CONFIG_CHOICE_APIC_AUTO=y
CONFIG_CCX_APIC_MODE=0xFF
CONFIG_CHOICE_NUMCCD_AUTO=y
CONFIG_CCX_CCD_MODE=0
CONFIG_CCX_SMT_MODE=1
CONFIG_CCX_CSTATE_ENABLE=1
CONFIG_CCX_CSTATE_IO_ADDR=0x0813
CONFIG_CCX_CSTATE_CC6_ENABLE=1
CONFIG_CCX_CPB_ENABLE=1
CONFIG_CCX_SMEE_ENABLE=0

# end of Compute Core Complex (CCX) Device

CONFIG_HAVE_NBIO_IOD=y

#
# IOAPIC settings
#
CONFIG_IOAPIC_MMIO_ADDRESS_RESERVED_ENABLE=1
CONFIG_IOAPIC_ID_PREDEFINE_EN=0
CONFIG_IOAPIC_ID_BASE=0xF1
# end of IOAPIC settings

CONFIG_CHOICE_AUTO=y
# CONFIG_CHOICE_DISABLED is not set
CONFIG_NBIO_GLOBAL_CG_OVERRIDE=0x0f
CONFIG_SSTUNL_CLK_GATING=1
CONFIG_NBIF_MGCG_CLK_GATING=1
CONFIG_NBIF_MGCG_HYSTERESIS=0
CONFIG_SYSHUB_MGCG_CLK_GATING=0
CONFIG_SYSHUB_MGCG_HYSTERESIS=0
CONFIG_IOHC_CLK_GATING_SUPPORT=1
CONFIG_NTB_CLOCK_GATING_ENABLE=1
CONFIG_IOHC_PG_ENABLE=1
CONFIG_IOHC_NONPCI_BAR_INIT_DBG=0
CONFIG_IOHC_NONPCI_BAR_INIT_FAST_REG=0
CONFIG_IOHC_NONPCI_BAR_INIT_FAST_REGCTL=0
# end of NBIO PMM - General

#
# NBIO common Options
#
CONFIG_IOMMU_SUPPORT=1
CONFIG_IOMMU_L1_CLOCK_GATING_EN=1
CONFIG_IOMMU_L2_CLOCK_GATING_EN=1
CONFIG_IOMMU_AVIC_SUPPORT=0
CONFIG_IOMMU_MMIO_ADDRESS_RESERVED_ENABLE=1
CONFIG_PCIE_ECRC_ENABLEMENT=1
CONFIG_AUTO_SPEED_CHANGE_EN=0
CONFIG_PCIE_ARI_SUPPORT=1
CONFIG_RX_MARGIN_PERSISTENCE_MODE=1
# end of NBIO common Options

#
# Advanced Error Reporting
#
CONFIG_AER_ENABLE=1
CONFIG_ACS_ENABLE=1
CONFIG_PCIE_LTR_ENABLE=1
CONFIG_TPH_COMPLETER_ENABLE=1
CONFIG_SRIOV_EN_DEV0F1=0
CONFIG_ARI_EN_DEV0F1=0
CONFIG_AER_EN_DEV0F1=0
CONFIG_ACS_EN_DEV0F1=0
CONFIG_ATS_EN_DEV0F1=0
CONFIG_PASID_EN_DEV0F1=0
CONFIG_RTR_EN_DEV0F1=0
CONFIG_PRI_EN_DEV0F1=0
CONFIG_ATC_ENABLE=0
CONFIG_ACS_EN_RCC_DEV0=0
CONFIG_AER_EN_RCC_DEV0=0
CONFIG_ACS_SOURCE_VAL_STRAP5=1
CONFIG_ACS_TRANSLATIONAL_BLOCKING_STRAP5=1
CONFIG_ACS_P2P_REQ_STRAP5=1
CONFIG_ACS_P2P_COMP_STRAP5=1
CONFIG_ACS_UPSTREAM_FWD_STRAP5=1
CONFIG_ACS_P2P_EGRESS_STRAP5=0
CONFIG_ACS_DIRECT_TRANSLATED_STRAP5=1
CONFIG_ACS_SSID_EN_STRAP5=1
CONFIG_DLF_EN_STRAP1=1
CONFIG_PHY_16GT_STRAP1=1
CONFIG_MARGIN_EN_STRAP1=1
CONFIG_PRI_EN_PAGE_REQ=1
CONFIG_PRI_RESET_PAGE_REQ=1
CONFIG_ACS_SOURCE_VAL=1
CONFIG_ACS_TRANSLATIONAL_BLOCKING=0
CONFIG_ACS_P2P_REQ=1
CONFIG_ACS_P2P_COMP=1
CONFIG_ACS_UPSTREAM_FWD=1
CONFIG_ACS_P2P_EGRESS=0
CONFIG_AMD_MASK_DPC_CAPABILITY=0
# end of Advanced Error Reporting

CONFIG_CHOICE_PCIE_SPEEDCTRL_AUTO=y
CONFIG_PCIE_SPEED_CONTROL=0x0F
CONFIG_PWR_EN_DEV0F1=0
CONFIG_TLP_PREFIX_SETTING=0
CONFIG_RCC_DEV0_EXTENDED_FMT_SUPPORTED=0
CONFIG_DLF_CAP_EN=1
CONFIG_DL_FEX_EN=1
CONFIG_PRE_CODE_REQUEST_ENABLE=0
CONFIG_ADVERTISE_EQ_TO_HIGH_RATE_SUPPORT=0
CONFIG_FABRIC_SDCI=0
CONFIG_ESM_EN_ALL_ROOT_PORTS=0
# end of Northbridge IO (NBIO) Device

CONFIG_HAVE_MPIO=y

#
# MicroProcessor Input Output (MPIO)
#
CONFIG_MPIO_CLOCKGATING_ENABLE=1
CONFIG_MPIO_TIMINGCTRL_ENABLE=0
CONFIG_PCIE_LINK_RECEIVER_DETECT_TIMEOUT=0
CONFIG_PCIE_LINK_RESET_TO_TRAINING_TIMEOUT=0
CONFIG_PCIE_LINK_L0_STATE_TIMEOUT=0
CONFIG_MPIO_EXACT_MATCH_ENABLE=0
CONFIG_MPIO_PHY_VALID=1
CONFIG_MPIO_PHY_PROGRAMMING=1
CONFIG_MPIO_SKIP_PSP_MSG=1
CONFIG_CHOICE_SAVE_RESTORE_MODE_DEFAULT=y
CONFIG_MPIO_SAVE_RESTORE_MODE=0xFF
CONFIG_CHOICE_ENABLE_PCIE_POLLING=y
CONFIG_MPIO_ALLOW_PCIE_POLLING=0x00
CONFIG_CHOICE_HOT_PLUG_AUTO=y
CONFIG_MPIO_HOT_PLUG_MODE=0xFF
CONFIG_CHOICE_PCIE_SRIS_AUTO=y
CONFIG_MPIO_PCIE_SRIS_CONTROL=0xFF
CONFIG_CHOICE_PCIE_SRIS_SKIP_INTERVAL_0=y
CONFIG_MPIO_PCIE_SRIS_SKIP_INTERVAL=0x00
CONFIG_MPIO_SRIS_SKIP_INTERVAL_SELECT=1
CONFIG_MPIO_SRIS_CONFIG_TYPE=0
CONFIG_CHOICE_SRIS_AUTO_DETECT_MODE_AUTO=y
CONFIG_MPIO_SRIS_AUTO_DETECT_MODE=0x0F
CONFIG_MPIO_SRIS_AUTODETECT_FACTOR=0
CONFIG_CHOICE_SRIS_SKP_TRANSMISSION_UNSUPPORTED=y
CONFIG_MPIO_PCIE_SRIS_SKP_TRANSMISSION_CONTROL=0x00
CONFIG_CHOICE_SRIS_SKP_RECEPTION_UNSUPPORTED=y
CONFIG_MPIO_PCIE_SRIS_SKP_RECEPTION_CONTROL=0x00
CONFIG_MPIO_CXL_PORT_CONTROL=1
CONFIG_MPIO_CXL_CORRECTABLE_ERROR_LOGGING=1
CONFIG_MPIO_CXL_UNCORRECTABLE_ERROR_LOGGING=1
CONFIG_MPIO_ADVANCED_ERROR_REPORTING_ENABLE=1
CONFIG_MPIO_PCIE_MULTICAST_ENABLE=0
CONFIG_MPIO_RECEIVE_ERROR_ENABLE=0
CONFIG_MPIO_EARLY_BMC_LINK_TRAIN_ENABLE=1
CONFIG_CHOICE_SOCKET_NUM_0=y
CONFIG_MPIO_EARLY_BMC_LINK_SOCKET=0x00
CONFIG_MPIO_EARLY_BMC_LINK_LANE=134
CONFIG_CHOICE_LANE_0_TO_31=y
CONFIG_MPIO_EARLY_BMC_LINK_DIE=0x00
CONFIG_MPIO_SURPRISE_DOWN_ENABLE=1
CONFIG_MPIO_PCIE_LINK_TRAINING_SPEED=0
CONFIG_MPIO_RX_MARGIN_ENABLE=1
CONFIG_MPIO_PCIE_CV_TEST_CONFIG=1
CONFIG_MPIO_PCIE_ARI_SUPPORT=1
CONFIG_MPIO_TOGGLE_NBIO_TO_SC=0
CONFIG_MPIO_TOGGLE_NBIO_IGNORE_CTO_ERROR=1
CONFIG_NBIO_CONTROLLER_SSID=0
CONFIG_IOMMU_CONTROLLER_SSID=0
CONFIG_PSP_CCP_CONTROLLER_SSID=0
CONFIG_NTB_CCP_CONTROLLER_SSID=0
CONFIG_NBIF0_CONTROLLER_SSID=0
CONFIG_NTB_CONTROLLER_SSID=0
CONFIG_PCIE_SUBSYSTEM_DEVICE_ID=0
CONFIG_PCIE_SUBSYSTEM_VENDOR_ID=0
CONFIG_MPIO_GPP_ATOMIC_OPS=1
CONFIG_MPIO_GPFXATOMIC_OPS=1
CONFIG_MPIO_EDB_ERROR_REPORTING_ENABLE=0
CONFIG_MPIO_OPN_SPARE=0
CONFIG_AMD_PRE_SIL_CONTROL=0
CONFIG_MPIO_ANCILLARY_DATA_SUPPORT_ENABLE=0
CONFIG_MPIO_AFTER_RESET_DELAY=0
CONFIG_MPIO_EARLY_LINK_TRAINING_ENABLE=0
CONFIG_CHOICE_USE_PLATFORM_CONFIG_DEFAULT=y
CONFIG_MPIO_EXPOSE_UNUSED_PCIE_PORTS=0xFF
CONFIG_CHOICE_NO_LINK_SPEED_LIMIT=y
CONFIG_MPIO_MAX_PCIE_LINK_SPEED=0
CONFIG_MPIO_SATA_PHY_TUNING=0
CONFIG_PCIE_LINK_COMPILANCE_MODE_ENABLE=1
CONFIG_MPIO_MCTP_SUPPORT_ENABLE=0
CONFIG_SBR_BROKEN_LANE_AVOIDANCE_ENABLE=1
CONFIG_AUTO_FULL_MARGINING_SUPPORT_ENABLE=1
CONFIG_GEN3_PCIE_PRESET_MASK=0xFFFFFFFF
CONFIG_GEN4_PCIE_PRESET_MASK=0xFFFFFFFF
CONFIG_GEN5_PCIE_PRESET_MASK=0xFFFFFFFF
CONFIG_CHOICE_ACTIVE_STATE_PWR_MGMT_AUTO=y
CONFIG_PCIE_LINK_ACTIVE_STATE_PWR_MGMT=0xFF
CONFIG_MCTP_MASTER_PCI_ADDR_SEGMENT=0
CONFIG_MCTP_MASTER_PCI_ADDR=0
# end of MicroProcessor Input Output (MPIO)

CONFIG_HAVE_SDCI=y

#
# Smart Data Cache Injection (SDCI)
#
CONFIG_SDCI_SMART_DATA_CACHE_INJECTION_ENABLE=0
# end of Smart Data Cache Injection (SDCI)
# end of AMD Silicon Feature Settings

# CONFIG_HAVE_EXAMPLE is not set
